1. Technical Field
The embodiments described herein relate to a semiconductor device, and more particularly, to a power noise detecting device and a power noise control device using the same.
2. Related Art
A power distribution network (PDN) is configured between a semiconductor integrated circuit (IC) device and an external apparatus to supply power to the semiconductor IC device from the external apparatus through the power distribution network. Parasitic components, such as capacitances, inductances, resistances, and the like, exist on the power distribution network. Accordingly, the parasitic components may have an negative influence on the proper operation of the semiconductor IC device. For example, the parasitic components may cause noise to be generated in the supplied power. Accordingly, a circuit is design to minimize the above-described parasitic components. One method includes use of a decoupling capacitor installed between power lines at a predetermined interval. However, the installation of the decoupling capacitor for reducing the parasitic components causes another parasitic component called an Equivalent Series Resistance (ESR) to be generated.
If the ESR is small, power distribution performance in a high-frequency region may be improved, but in a resonance frequency region between a semiconductor IC chip and a package covering the chip, as the ESR becomes smaller, the power noise becomes larger. Accordingly, it is necessary to optimize the ESR by considering various operational environments of the semiconductor IC. As a result, it is necessary to accurately detect the power noise.
However, since the semiconductor IC is commonly designed only to minimize the ESR, there is a problem in that the power noise cannot be reduced to a desired level. Furthermore, an analog/digital converter or a delay line is commonly used to detect the power noise for the purpose of controlling the ESR. However, a large circuit area is required to implement the analog/digital converter or the delay line, which causes a loss in layout area while increasing power consumption.